FIG. 1 shows a synchronous buck converter 10, in which a transistor M1 is connected between a power input VIN and a phase node PH, a transistor M2 is connected between the phase node PH and ground GND, and a controller 12 provides control signals UG and LG to switch the transistors M1 and M2 so as to generate an inductor current I flowing through an inductor L to charge a capacitor Co to produce an output voltage VOUT. In the traditional synchronous buck converter 10, the transistors M1 and M2 for serving as power switches are packaged in two individual packages, respectively, and therefore need much space. In order to reduce the needed space, it has been proposed to package the two transistors M1 and M2 in a single package.
FIG. 2 shows a traditional dual SO-8 MOSFET package 20, in which the drain D1 of the MOS transistor M1 is connected to the pins 5 and 6, the source S1 of the MOS transistor M1 is connected to the pin 3, the gate G1 of the MOS transistor M1 is connected to the pin 4, the drain D2 of the MOS transistor M2 is connected to the pins 7 and 8, the source S2 of the MOS transistor M2 is connected to the pin 1, the gate G2 of the MOS transistor M2 is connected to the pin 2, and a plastic body 21 encapsulates the transistors M1 and M2. FIG. 3 shows a top perspective view of the SO-8 package 20 shown in FIG. 2, there are eight pins in this package 20, and a recess 22 on the top of the package 20 to indicate the position of the pin 1, FIG. 4 shows a layout when the package 20 is used in a synchronous buck converter, in which the pin 1 of the package 20 is connected to ground GND by a wire 24, the pin 2 of the package 20 is connected with the control signal LG by a wire 26, the pin 3 of the package 20 is connected to the pins 7 and 8 of the package 20 by a wire 28, the pin 4 of the package 20 is connected with the control signal UG by a wire 30, and the pins 5 and 6 of the package 20 are connected to the power input VIN by a wire 32. Although the transistors M1 and M2 are integrated in the single package 20 to reduce the needed space, it brought more inconvenience and difficulty in the layout of the printed circuit board (PCB). For example, the wire 28 needs across over the two wires 24 and 26 to connect the source S1 of the transistor M1 to the drain D2 of the transistor M2.
In order to reduce the difficulty in the PCB layout, FairChild Semiconductor Corporation has developed two dual SO-8 MOSFET packages, with the product numbers FD6900AS and FD6986AS. In addition, International Rectifier (IR) Corporation also has developed a dual SO-8 MOSFET package, with the product number IRF7094. In these packages, the connection between the source S1 of the transistor M1 and the drain D of the transistor M2 is within the packages.
FIG. 5 shows a layout when a FairChild FD6900AS is used in a synchronous buck converter. In the package 40, the drain D1 of the transistor M1 is connected to the power input VIN via the pins 1 and 2, the source S1 of the transistor M1 is connected to the inductor L via the pins 5, 6 and 7, the gate G1 of the transistor M1 is connected with the control signal UG via the pin 8, the connection between the drain D2 of the transistor M2 and the source S1 of the transistor M1 is within the package 40, the source S2 of the transistor M2 is grounded via the pin 4, the gate G2 of the transistor M2 is connected with the control signal LG via the pin 3, and a plastic body 42 encapsulates the transistors M1 and M2.
FIG. 6 shows a layout when a FairChild FD6986AS is used in a synchronous buck converter. In the package 50, the drain D1 of the transistor M1 is connected to the power input VIN via the pins 7 and 8, the source S1 of the transistor M1 is connected to the inductor L via the pins 1, 5 and 6, the gate G1 of the transistor M1 is connected with the control signal UG via the pin 2, the connection between the drain D2 of the transistor M2 and the source S1 of the transistor M1 is within the package 50, the source S2 of the transistor M2 is grounded via the pin 3, the gate G2 of the transistor M2 is connected with the control signal LG via the pin 4, and a plastic body 52 encapsulates the transistors M1 and M2.
FIG. 7 shows a layout when an IRF7094 is used in a synchronous buck converter. In the package 60, the drain D1 of the transistor M1 is connected to the power input VIN via the pin 8, the source S1 of the transistor M1 is connected to the inductor L via the pins 5, 6 and 7, the gate G1 of the transistor M1 is connected with the control signal UG via the pin 1, the connection between the drain D2 of the transistor M2 and the source S1 of the transistor M1 is within the package 60, the source S2 of the transistor M2 is grounded via the pins 2 and 3, the gate G2 of the transistor M2 is connected with the control signal LG via the pin 4, and a plastic body 62 encapsulates the transistors M1 and M2.
In the PCB layout, however, these packages 40, 50 and 60 still bring disadvantages. For example, when using the package 40, the wire (from the pin 3) for the gate G2 of the transistor M2 to connect with the control signal LG needs across over another wire; and when using the package 50, the wire (from the pin 2) for the gate G1 of the transistor M1 to connect with the control signal UG needs across over another wire. When using the package 60, the pin 8 which is connected to the power supply VIN isn't on the same side of the package 60 as that for the pins 2 and 3 which are connected to ground GND, and therefore the cathode of the input capacitor Cin which is connected to the power input VIN needs across over another wire to connect to ground GND, increasing the difficulty for the layout. An alternative solution to avoid such layout issue is to add a through hole in the PCB for the cathode of the input capacitor Cin to connect to the ground plane on the back surface of the PCB via the through hole. However, such approach will reduce the decoupling capability of the input capacitor Cin.
On the other hand, when a dual MOSFET package is operating, heat will be generated on the I/O terminals of the transistors M1 and M2 within the package. Most of the heat will be transferred to the PCB through the pins which are connected to the terminals of the transistors M1 and M2, and then dissipated to the air from the PCB. Unfortunately, in a traditional dual MOSFET package, the connections between the terminals of the transistors M1 and M2 and the pins are implemented by bonding wires which are very thin, and therefore the heat on some of the terminals which have higher heat density cannot be quickly transferred to the PCB. For example, the drain D1 which is connected to the power input VIN and the source S1 and drain D2 which output the inductor current I connot quickly transfer the heat thereon to the pins they are connected to for further dissipating to the PCB. As a result, the dual MOSFET package connot be applied to some devices which need larger inductor current, for example motherboard, due to the poor thermal dissipation of the package.
Therefore, a dual MOSFET package convenient for layout and advantageous for thermal dissipation is desired.